This application is based upon and claims priority from prior French Patent Application No. 0010727, filed on Aug. 18, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits and more particularly to the production of xe2x80x9cmetal-metalxe2x80x9d capacitors.
2. Description of the Prior Art
Among the various types of capacitor that can appear within an integrated circuit on a semiconductor chip, for example a silicon chip, mention may be made of capacitors known as xe2x80x9cpolysilicon-siliconxe2x80x9d, xe2x80x9cpolysilicon-polysiliconxe2x80x9d or xe2x80x9cmetal-metalxe2x80x9d capacitors, depending on the composition of their electrodes.
Capacitors known as xe2x80x9cmetal-metalxe2x80x9d capacitors, that is to say those in which the two electrodes are made of metal, allow capacitors of high capacitance to be produced and offer the advantage of having a very small variation in the capacitance depending on the voltage that is applied to them. Furthermore, they have a very small resistive component. Thus, xe2x80x9cmetal-metalxe2x80x9d capacitors are advantageously used in radio-frequency applications.
An integrated circuit generally comprises electronic components, for example transistors, produced within a semiconductor substrate, and various metallization levels making it possible in particular to produce interconnect tracks between the various components of the integrated circuit. Each metallization level then generally has, after a metal layer has been etched, several interconnect tracks located at this same level that are mutually separated by an intertrack insulating layer. The metallization level immediately above is then produced on an interlevel insulating layer covering the lower metallization level. Interconnection between tracks located at two adjacent metallization levels is achieved by interconnect holes filled with a fill metal, for example tungsten, and usually called by those skilled in the art xe2x80x9cviasxe2x80x9d.
A known process for fabricating a metal-metal capacitor within an integrated circuit consists in producing one of the electrodes of the capacitor at the same time as all of the interconnect tracks of a given metallization level. On this given metallization level is then deposited an interlevel insulating layer intended to support the metallization level immediately above it. An aperture emerging above the first electrode of the capacitor is then etched in this interlevel insulating layer and then a thin layer of dielectric, for example generally silicon dioxide or possibly silicon nitride, is then deposited. The aperture is then filled, by deposition followed by planarization, with fill metal, typically tungsten. Next, the metal layer of the metallization level immediately above is deposited and etched so as to produce the interconnect tracks of this metallization level, and the second electrode of the metal-metal capacitor.
In other words, according to this solution, the two electrodes of the metal-metal capacitor are produced on two metallization levels.
In other solutions, provisions are made to produce the two electrodes of the metal-metal capacitor using a single conducting level.
Thus, in French Patent Application No. 2 766 294, the two metal electrodes and the dielectric layer of the capacitor are produced virtually on one metallization level, the lower electrode of the capacitor resulting from etching of the metal layer intended to form the various tracks of the metallization level.
U.S. Pat. No. 6,008,083 describes another way of producing a metal-metal capacitor whose two electrodes are produced within the same interlevel insulating layer. However, the production of such a capacitor requires, prior to the production of the lower electrode, the formation of a pad contacting this lower electrode and produced within the lower metallization level.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
The aim of the invention is to produce a metal-metal capacitor using a single conducting level, but according to a process which is completely different from those used in the prior art and especially requiring no formation, prior to that of the first electrode, of a contact pad allowing connection to the lower electrode.
According to an aspect of the invention a preferred embodiment provides production processes that are compatible with a process of the xe2x80x9cdamascenexe2x80x9d type using the term well known to those of ordinary skill in the art.
According to an aspect of the invention a preferred embodiment provides a process that allows the production, at the same level, of a capacitor and of a metal track belonging to this metallization level.
A subject of the invention is therefore a process for fabricating an integrated circuit, comprising the production of several metallization levels, which are mutually separated by interlevel insulating layers, and of intertrack insulating layers each separating the tracks of the same metallization level. The process also comprises the production of at least one capacitor comprising a lower electrode and an upper electrode which are mutually separated by a dielectric layer.
According to a preferred embodiment of the invention, the production of the capacitor comprises:
the simultaneous production, in at least part of an intertrack insulating layer associated with a given metallization level, on the one hand, of the two electrodes and of the dielectric layer of the capacitor and, on the other hand, of a conducting trench which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor; and
the production, in the interlevel insulating layer covering the intertrack insulating layer, of two conducting pads which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.
In other words, the invention, by simultaneously producing the capacitor and the lateral trench, provides for the contacting of the two electrodes of the capacitor from the top of the integrated circuit. The invention therefore in no way requires the formation, prior to that of the capacitor, of a lower contact pad for connection to the lower electrode.
According to one method of implementing the process according to the invention, the production of the capacitor and of the trench comprises:
a) the formation of the intertrack insulating layer on an interlevel insulating layer;
b) the etching of at least part of the intertrack insulating layer so as to form a cavity having a main part laterally extended by the trench;
c) the formation of a first layer of a first conducting material, for example copper or aluminium, on the structure obtained in step b) and the formation of a layer of a dielectric, for example silicon dioxide, on the first layer; and
d) the formation of a second layer of a second conducting material, for example also copper or aluminium, on the dielectric layer so as to fill the main part of the cavity, the dimensions of the trench and the thicknesses of the first layer and of the dielectric layer being chosen so as to obtain, after step d), a trench comprising at least the first conducting material but not containing the second conducting material (the trench possibly containing dielectric material);
e) chemical-mechanical polishing of the multilayer stack formed in steps c) and d) so as to leave, in the main part of the cavity, the capacitor whose lower electrode is formed from a residual part of the first layer coating the internal walls of the cavity and whose upper electrode is formed from a residual part of the second layer, which is separated from the residual part of the first layer by a residual part of the dielectric layer, and to leave, in the trench, another residual part of the first layer coating at least the internal walls of the trench, to the exclusion of any residual part of the second layer.
The first conducting layer and the dielectric layer are formed in step c) by a conformal coating. In this case, the width of the trench is preferably at least twice the thickness of the first conducting layer and less than twice the sum of the thickness of the first conducting layer and of the thickness of the dielectric layer.
Depending on the dimensions of the trench, the latter may comprise only the conducting material forming the first electrode, or possibly the conducting material forming the first layer and a residual part of the dielectric material.
The invention also makes it possible, advantageously, to produce the tracks of the given metallization level simultaneously with the formation of the upper electrode of the capacitor.
Thus, according to one method of implementing a preferred embodiment of the invention, the production of the tracks of the given metallization level comprises:
after step c), etching of the dielectric layer, of the first conducting layer and of the intertrack insulating layer so as to form at least one auxiliary trench (defining the location of a track);
the deposition of the second conducting layer carried out in step d) so as to fill the trench or trenches; and
the chemical-mechanical polishing carried out in step e) so as to remove the first conducting layer, the dielectric layer and the second conducting layer from the surface of the intertrack insulating layer.
The subject of the invention is also an integrated circuit comprising several metallization levels, which are mutually separated by interlevel insulating layers, and intertrack insulating layers each separating the tracks of the same metallization level. The integrated circuit also includes at least one capacitor comprising a lower electrode and an upper electrode that are mutually separated by a dielectric layer.
According to a general aspect of the invention, the capacitor is located in at least part of an intertrack insulating layer associated with a given metallization level. The lower electrode of the capacitor is laterally extended by a conducting trench that is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor. The integrated circuit also comprises, in the interlevel insulating layer covering the intertrack insulating layer, two conducting pads which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.
According to one embodiment of the integrated circuit according to the invention, the trench comprises only the conducting material forming the lower electrode.
In another embodiment of the invention, the trench may only comprise the dielectric encapsulated by the conducting material forming the lower electrode.
However, in all cases, the trench contains no conducting material forming the second electrode.
Moreover, the tracks of the given metallization level are advantageously formed from the same material as that forming the upper electrode of the capacitor.